technical data 251 presettable bcd/decade up/down counter high-performance silicon-gate cmos the in74hc192 is identical in pinout to the ls/als192. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with ls/alsttl outputs. the counter has two separate clock inputs, a count up clock and count down clock inputs. the direction of counting is determined by which input is clocked. the outputs change state synchronous with the low-to-high transitions on the clock inputs. this counter may be preset by entering the desired data on the p0, p1, p2, p3 input. when the parallel load input is taken low the data is loaded independently of either clock input. this feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. in addition the counter can also be cleared. this is accomplished by inputting a high on the master reset input. all 4 internal stages are set to low independently of either clock input.both a terminal count down (tc d ) and terminal count up (tc u ) outputs are provided to enable cascading of both up and down counting functions. the tc d output produces a negative going pulse when the counter underflows and tc u outputs a pulse when the counter overflows. the counter can be cascaded by connecting the tc u and tc d outputs of one device to the count up clock and count down clock inputs, respectively, of the next device. ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices in74hc192 ordering information IN74HC192N plastic in74hc192d soic t a = -55 to 125 c for all packages pin assignment logic diagram pin 16 =v cc pin 8 = gnd
in74hc192 252 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c t r , t f input rise and fall time (figure 1) v cc =2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74hc192 253 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to -55 c 85 c 125 c unit v ih minimum high-level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low - level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v v oh minimum high-level output voltage v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low-level output voltage v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in =v ih or v il ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 a 6.0 8.0 80 160 a function table inputs mode mr pl cp u cp d hx x x reset(asyn.) l l x x preset(asyn.) l h h no count l h h count up l h h count down l h h no count x = don?t care the in74hc192 can be preset to any state, but will not count beyond 9. if preset to state 10, 11, 12, 13, 14 or 15, it will follow the sequence 10, 11, 6: 12, 13, 4: 14, 15, 2 if counting up, and follow the sequence 15, 14, 13, 12, 11, 10, 9 if counting down. logic equations for terminal count: tc u = q 0 ? q 3 ? cp u tc d = q 0 ? q 1 ? q 2 ? q 3 ? cp d
in74hc192 254 ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit f max minimum clock frequency (50% duty cycle) (figures 1 and 6) 2.0 4.5 6.0 12 36 43 3.2 16 19 2.6 13 15 mhz t plh , t phl maximum propagation delay, clock to q (figures 1 and 6) 2.0 4.5 6.0 215 43 37 270 54 46 325 65 55 ns t plh , t phl maximum propagation delay, pl to q (figures 3 and 6) 2.0 4.5 6.0 215 43 37 270 54 46 325 65 55 ns t plh , t phl maximum propagation delay, clock to terminal count (figures 2 and 6) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns t tlh , t thl maximum output transition time,any output (figures 1 and 6) 2.0 4.5 6.0 75 15 13 95 20 18 110 23 20 ns c in maximum input capacitance - 10 10 10 pf power dissipation capacitance (per package) typical @25 c,v cc =5.0 v c pd used to determine the no-load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 60 pf timing requirements (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit t su minimum setup time, pn to pl (figure 4) 2.0 4.5 6.0 100 20 18 125 35 22 150 30 26 ns t h minimum hold time, pn to pl (figure 4) 2.0 4.5 6.0 0 0 0 0 0 0 0 0 0 ns t w minimum pulse width, clock (figure 1) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns t w minimum pulse width, pl (figure 3) 2.0 4.5 6.0 100 20 17 125 25 26 150 30 26 ns t w minimum pulse width, mr (figure 5) 2.0 4.5 6.0 100 20 17 125 25 26 150 30 26 ns t r , t f minimum input rise and fall times (figure 1) 2.0 4.5 6.0 100 500 400 100 500 400 100 500 400 ns
in74hc192 255 figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms figure 4. switching waveforms figure 5. switching waveforms figure 6. test circuit
in74hc192 256 timing diagram
in74hc192 257 expanded logic diagram
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